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NVIDIA A100 SXM4 80GB

SXM In production Released 2020 ampere
BF16
TFLOP/s
312 厂商声称
FP8
TFLOP/s
unsupported
FP4
TFLOP/s
unsupported
Memory
GB
80 厂商声称
Mem BW
GB/s
2039 厂商声称
TDP
W
400 厂商声称

Full specs

Compute

FP4 TFLOPS
unsupported
FP8 TFLOPS
unsupported
BF16 TFLOPS
312
FP16 TFLOPS
312
INT8 TOPS
624

Memory

Capacity
80 GB
Bandwidth
2039 GB/s
Type
HBM2e

Die architecture 🟢 vendor floorplan

SM count
108
Tensor cores / SM
4
L2 cache
40 MB
HBM stacks
5
Process
7 nm
Die area
826 mm²
Transistors
54 B
PCIe
Gen 4 ×16

Scale-Up (intra-node)

Protocol
NVLink-3.0
Per-link BW
600 GB/s
World size
8
Topology
switched
Switch
nvswitch-gen2

Scale-Out (inter-node)

Per-card NIC
200 Gbps
Protocol
InfiniBand-HDR
NIC
ConnectX-6

Topology

拓扑结构 · Topology
8 卡 scale-up domain
芯片内部 / Die-level architecture
HBM HBM HBM HBM HBM NVIDIA A100 SXM4 80GB L2 / shared cache · NoC L1$ / register file (per SM) 108 SMs · darker block = tensor / matrix engine 312 TFLOPS BF16 · 80 GB HBM2e @ 2.0 TB/s · 400 W TDP

🟢 vendor floorplan 108 SMs · 5× HBM · 40 MB L2 · 7 nm · 54 B transistors · 826 mm²


集群拓扑 / Cluster topology · NVLink-3.0 @ 600 GB/s
nvswitch-gen2 600 GB/s/link · all-to-all GPU 0 80GB GPU 1 80GB GPU 2 80GB GPU 3 80GB GPU 4 80GB GPU 5 80GB GPU 6 80GB GPU 7 80GB 8 cards · switched topology · scale-out: 200 Gbps/card
Scale-Up · 域内
NVLink-3.0
600 GB/s · 拓扑: switched
world_size = 8
Scale-Out · 跨域
InfiniBand-HDR
200 Gbps/卡 NIC
ConnectX-6

Which models can it run?

Quick estimates · decode tok/s/card 上界

TP=8 · BF16 · batch=16 · prefill=1024 · decode=256 · 已应用 efficiency 校准

在计算器中调整 →
模型 参数 (active) Decode tok/s/card 瓶颈
DeepSeek V4 Pro
deepseek
49B 显存不足
DeepSeek V4 Flash
deepseek
13B 174 内存带宽
Mistral Small 4
mistral
22B 79 内存带宽
GLM-5 Reasoning
zhipu
32B 66 内存带宽
GLM-5.1
zhipu
32B 显存不足
Qwen3.6 Plus
alibaba
35B 显存不足
Kimi K2.6
moonshot
32B 显存不足
MiniMax M2.7
minimax
46B 显存不足

Operator-level fit · per-model bottleneck + upper bound

算子级 fit · operator-level fit (per-token roofline)

基于每个模型 operator_decomposition + 本卡 BF16 312 TFLOPS / 2,039 GB/s 计算 · ridge point ≈ 153 FLOPs/byte

上界 = min(计算屋顶, 内存带宽屋顶) · efficiency 未应用
模型 domain 主导算子 AI · F/B 瓶颈 tok/s 上界
DeepSeek V4 Pro llm matmul 245.5 🔥 计算 52k
GraphCast scientific graph-message-passing 0.9 💾 内存带宽 3762
AlphaFold 3 scientific pair-bias-attention 2.3 💾 内存带宽 1130
GPT-OSS llm matmul 0.7 💾 内存带宽 165
Gemma 4 26B llm matmul 0.7 💾 内存带宽 123
DeepSeek V4 Flash llm matmul 0.8 💾 内存带宽 116
Mistral Small 4 llm matmul 0.6 💾 内存带宽 53
Llama 4 Maverick llm matmul 0.8 💾 内存带宽 52
需要 efficiency 校准 + concurrency 扫描 + TCO 估算 → 在计算器中评估 →

Operator support & optimization headroom

算子支持 & 优化空间 / Operator support & headroom

Per-operator support derived from software_support.engines + scale-up topology. Optimization headroom from measured efficiency factor.

Optimization headroom
+-50 pp
saturated

Near saturation at 150% of roofline. Further gains require workload restructure (disaggregated, speculative, smaller batch).

Communication (collective)
All-to-All 🟢 mature
all-to-all via NVLink-3.0 world_size=8
AllReduce 🟢 mature
NVLink-3.0 ring all-reduce
Attention
Multi-Head Attention 🟢 mature
paged-attention via vLLM/SGLang/MindIE
FlashAttention-3 🔴 gap
No FA-3 path; falls back to FA-2 / vanilla SDPA
Matrix multiply (GEMM)
Matrix Multiplication 🟢 mature
GEMM supported on all inference engines
MoE routing
MoE Routing 🟢 mature
MoE gating supported via vLLM ≥0.4 / SGLang
Normalization
RMSNorm 🟢 mature
fused into engine kernels
Embedding
fused into engine kernels
Activation
SiLU / Swish 🟢 mature
fused into engine kernels
Softmax 🟢 mature
fused into engine kernels

Software-stack support

Engine Status BF16FP16FP4FP8 E4M3FP8 E5M2INT4 AWQ
HanGuangAI unconfirmed
LMDeploy official
MindIE unconfirmed
MoRI unconfirmed
SGLang official
TensorRT-LLM (Dynamo) official
vLLM official
Measured efficiency factor

Computed from 1 measured cases for this card. The calculator uses this value in place of the default 0.5.

1.50
measured / theoretical (n=1)

Existing deployment cases (1)

Citations

  1. [1] NVIDIA A100 Tensor Core GPU Datasheet (80GB SXM variant) — https://www.nvidia.com/en-us/data-center/a100/ · accessed 2026-04-28 厂商声称
  2. [2] NVIDIA Ampere Architecture Whitepaper (GA100 die: 108 SMs enabled, 40 MB L2, 54B transistors, 826 mm² @ TSMC 7nm) — https://images.nvidia.com/aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf · accessed 2026-04-28 厂商声称
⚠ A100 has no FP8 native (Hopper+); FP8 only via emulated paths.
⚠ All performance figures are vendor-claimed unless tier=measured.