A AMD Last verified

AMD Instinct MI300X

OAM In production Released 2023 cdna3
BF16
TFLOP/s
1307 厂商声称
FP8
TFLOP/s
2614 厂商声称
FP4
TFLOP/s
unsupported
Memory
GB
192 厂商声称
Mem BW
GB/s
5300 厂商声称
TDP
W
750 厂商声称

Full specs

Compute

FP4 TFLOPS
unsupported
FP8 TFLOPS
2614
BF16 TFLOPS
1307
FP16 TFLOPS
1307
INT8 TOPS
2614

Memory

Capacity
192 GB
Bandwidth
5300 GB/s
Type
HBM3

Die architecture 🟢 vendor floorplan

CU count
304
L2 cache
256 MB
HBM stacks
8
Process
5 nm
Die area
1017 mm²
Transistors
153 B
PCIe
Gen 5 ×16

Scale-Up (intra-node)

Protocol
Infinity-Fabric
Per-link BW
896 GB/s
World size
8
Topology
fully-connected
Switch
—

Scale-Out (inter-node)

Per-card NIC
400 Gbps
Protocol
RoCEv2
NIC
—

Topology

拓扑结构 · Topology
8 卡 scale-up domain
芯片内部 / Die-level architecture
HBM HBM HBM HBM HBM HBM HBM HBM AMD Instinct MI300X L2 / shared cache · NoC L1$ / register file (per CU) 304 CUs · darker block = tensor / matrix engine 1307 TFLOPS BF16 · 2614 FP8 · 192 GB HBM3 @ 5.3 TB/s · 750 W TDP

🟢 vendor floorplan 304 CUs · 8× HBM · 256 MB L2 · 5 nm · 153 B transistors · 1017 mm²

集群拓扑 / Cluster topology · Infinity-Fabric @ 896 GB/s
Infinity-Fabric switch 896 GB/s/link · all-to-all GPU 0 192GB GPU 1 192GB GPU 2 192GB GPU 3 192GB GPU 4 192GB GPU 5 192GB GPU 6 192GB GPU 7 192GB 8 cards · fully-connected topology · scale-out: 400 Gbps/card
Scale-Up · 域内
Infinity-Fabric
896 GB/s · 拓扑: fully-connected
world_size = 8
Scale-Out · 跨域
RoCEv2
400 Gbps/卡 NIC

Which models can it run?

Quick estimates · decode tok/s/card 上界

TP=8 · FP8 · batch=16 · prefill=1024 · decode=256 · 已应用 efficiency 校准

在计算器中调整 →
模型 参数 (active) Decode tok/s/card 瓶颈
DeepSeek V4 Pro
deepseek
 49B — 显存不足
DeepSeek V4 Flash
deepseek
 13B 452 内存带宽
Mistral Small 4
mistral
 22B 206 内存带宽
GLM-5 Reasoning
zhipu
 32B 171 内存带宽
GLM-5.1
zhipu
 32B 116 内存带宽
Qwen3.6 Plus
alibaba
 35B 111 内存带宽
Kimi K2.6
moonshot
 32B 95 内存带宽
MiniMax M2.7
minimax
 46B 75 内存带宽

Operator-level fit · per-model bottleneck + upper bound

算子级 fit · operator-level fit (per-token roofline)

基于每个模型 operator_decomposition + 本卡 BF16 1,307 TFLOPS / 5,300 GB/s 计算 · ridge point ≈ 247 FLOPs/byte

上界 = min(计算屋顶, 内存带宽屋顶) · efficiency 未应用
模型 domain 主导算子 AI · F/B 瓶颈 tok/s 上界
DeepSeek V4 Pro llm matmul 245.5 💾 内存带宽 216k
GraphCast scientific graph-message-passing 0.9 💾 内存带宽 9779
AlphaFold 3 scientific pair-bias-attention 2.3 💾 内存带宽 2938
GPT-OSS llm matmul 0.7 💾 内存带宽 428
Gemma 4 26B llm matmul 0.7 💾 内存带宽 318
DeepSeek V4 Flash llm matmul 0.8 💾 内存带宽 301
Mistral Small 4 llm matmul 0.6 💾 内存带宽 137
Llama 4 Maverick llm matmul 0.8 💾 内存带宽 136
需要 efficiency 校准 + concurrency 扫描 + TCO 估算 → 在计算器中评估 →

Operator support & optimization headroom

算子支持 & 优化空间 / Operator support & headroom

Per-operator support derived from software_support.engines + scale-up topology. Optimization headroom from measured efficiency factor.

Optimization headroom
+-50 pp
saturated

Near saturation at 150% of roofline. Further gains require workload restructure (disaggregated, speculative, smaller batch).

Communication (collective)
All-to-All 🟢 mature
all-to-all via Infinity-Fabric world_size=8
AllReduce 🟢 mature
Infinity-Fabric ring all-reduce
Attention
Multi-Head Attention 🟢 mature
paged-attention via vLLM/SGLang/MindIE
FlashAttention-3 🟢 mature
FA-3 on modern engine + tensor cores
Matrix multiply (GEMM)
Matrix Multiplication 🟢 mature
GEMM supported on all inference engines
MoE routing
MoE Routing 🟢 mature
MoE gating supported via vLLM ≥0.4 / SGLang
Normalization
RMSNorm 🟢 mature
fused into engine kernels
Embedding
Rotary Position Embedding 🟢 mature
fused into engine kernels
Activation
SiLU / Swish 🟢 mature
fused into engine kernels
Softmax 🟢 mature
fused into engine kernels

最接近的替代卡 (按规格相似度)

基于 BF16 算力 / 显存 / 显存带宽 / FP8 加权欧氏距离。供选型决策参考。

NVIDIA GB200 NVL72
NVIDIA
99%
相似度
BF16
2250
Mem
192
BW
8.0
NVIDIA B200 SXM 180GB
NVIDIA
99%
相似度
BF16
2250
Mem
180
BW
8.0
Etched Sohu
Etched
98%
相似度
BF16
1125
Mem
144
BW
5.8
NVIDIA H200 SXM 141GB
NVIDIA
98%
相似度
BF16
989
Mem
141
BW
4.8

Software-stack support

Engine Status BF16FP16FP4FP8 E4M3FP8 E5M2INT4 AWQ
HanGuangAI unconfirmed — — — — — —
LMDeploy unconfirmed — — — — — —
MindIE unconfirmed — — — — — —
MoRI unconfirmed — — — — — —
SGLang official ✓ ✓ — ✓ — ✓
TensorRT-LLM (Dynamo) unconfirmed — — — — — —
vLLM official ✓ ✓ — ✓ — ✓
Measured efficiency factor

Computed from 1 measured cases for this card. The calculator uses this value in place of the default 0.5.

1.50
measured / theoretical (n=1)

Existing deployment cases (1)

Citations

  1. [1] AMD MI300X product page — https://www.amd.com/en/products/accelerators/instinct/mi300/mi300x.html · accessed 2026-04-28 厂商声称
  2. [2] AMD CDNA 3 architecture: 304 CUs across 8 XCD chiplets, 256 MB Infinity Cache (L2), 8× HBM3 stacks @ 24 GB ⇒ 192 GB, 153B transistors @ TSMC 5nm + 6nm chiplets — https://www.amd.com/en/products/accelerators/instinct/mi300/mi300x.html · accessed 2026-04-28 厂商声称
⚠ All performance figures are vendor-claimed unless tier=measured.