H Hygon China Last verified

海光 DCU Z100

PCIE In production Released 2022 hygon-dcu-gen2
BF16
TFLOP/s
96 厂商声称
FP8
TFLOP/s
unsupported
FP4
TFLOP/s
unsupported
Memory
GB
64 厂商声称
Mem BW
GB/s
1024 厂商声称
TDP
W
350 厂商声称

Full specs

Compute

FP4 TFLOPS
unsupported
FP8 TFLOPS
unsupported
BF16 TFLOPS
96
FP16 TFLOPS
96
INT8 TOPS
192

Memory

Capacity
64 GB
Bandwidth
1024 GB/s
Type
HBM2e

Die architecture 🟢 vendor floorplan

CU count
64
HBM stacks
4
Process
7 nm
PCIe
Gen 4 ×16

Scale-Up (intra-node)

Protocol
PCIe-Gen4
Per-link BW
64 GB/s
World size
8
Topology
pcie-fabric
Switch
—

Scale-Out (inter-node)

Per-card NIC
100 Gbps
Protocol
RoCEv2
NIC
—

Topology

拓扑结构 · Topology
8 卡 scale-up domain
芯片内部 / Die-level architecture
HBM HBM HBM HBM 海光 DCU Z100 L2 / shared cache · NoC L1$ / register file (per CU) 64 CUs · darker block = tensor / matrix engine 96 TFLOPS BF16 · 64 GB HBM2e @ 1.0 TB/s · 350 W TDP

🟢 vendor floorplan 64 CUs · 4× HBM · 7 nm

集群拓扑 / Cluster topology · PCIe-Gen4 @ 64 GB/s
PCIe-Gen4 switch 64 GB/s/link · all-to-all GPU 0 64GB GPU 1 64GB GPU 2 64GB GPU 3 64GB GPU 4 64GB GPU 5 64GB GPU 6 64GB GPU 7 64GB 8 cards · pcie-fabric topology · scale-out: 100 Gbps/card
Scale-Up · 域内
PCIe-Gen4
64 GB/s · 拓扑: pcie-fabric
world_size = 8
Scale-Out · 跨域
RoCEv2
100 Gbps/卡 NIC

Which models can it run?

Quick estimates · decode tok/s/card 上界

TP=8 · FP16 · batch=16 · prefill=1024 · decode=256 · 已应用 efficiency 校准

在计算器中调整 →
模型 参数 (active) Decode tok/s/card 瓶颈
DeepSeek V4 Pro
deepseek
 49B — 显存不足
DeepSeek V4 Flash
deepseek
 13B — 显存不足
Mistral Small 4
mistral
 22B 13 内存带宽
GLM-5 Reasoning
zhipu
 32B 11 内存带宽
GLM-5.1
zhipu
 32B — 显存不足
Qwen3.6 Plus
alibaba
 35B — 显存不足
Kimi K2.6
moonshot
 32B — 显存不足
MiniMax M2.7
minimax
 46B — 显存不足

Operator-level fit · per-model bottleneck + upper bound

算子级 fit · operator-level fit (per-token roofline)

基于每个模型 operator_decomposition + 本卡 BF16 96 TFLOPS / 1,024 GB/s 计算 · ridge point ≈ 94 FLOPs/byte

上界 = min(计算屋顶, 内存带宽屋顶) · efficiency 未应用
模型 domain 主导算子 AI · F/B 瓶颈 tok/s 上界
DeepSeek V4 Pro llm matmul 245.5 🔥 计算 16k
GraphCast scientific graph-message-passing 0.9 💾 内存带宽 1889
AlphaFold 3 scientific pair-bias-attention 2.3 💾 内存带宽 568
GPT-OSS llm matmul 0.7 💾 内存带宽 83
Gemma 4 26B llm matmul 0.7 💾 内存带宽 62
DeepSeek V4 Flash llm matmul 0.8 💾 内存带宽 58
Mistral Small 4 llm matmul 0.6 💾 内存带宽 27
Llama 4 Maverick llm matmul 0.8 💾 内存带宽 26
需要 efficiency 校准 + concurrency 扫描 + TCO 估算 → 在计算器中评估 →

Operator support & optimization headroom

算子支持 & 优化空间 / Operator support & headroom

Per-operator support derived from software_support.engines + scale-up topology. Optimization headroom from measured efficiency factor.

Optimization headroom
+50 pp
moderate

No cases yet — using default 0.5 efficiency. Real headroom unknown until first measurement lands.

Communication (collective)
All-to-All 🟢 mature
all-to-all via PCIe-Gen4 world_size=8
AllReduce 🟢 mature
PCIe-Gen4 ring all-reduce
Attention
Multi-Head Attention 🟢 mature
paged-attention via vLLM/SGLang/MindIE
FlashAttention-3 🔴 gap
No FA-3 path; falls back to FA-2 / vanilla SDPA
Matrix multiply (GEMM)
Matrix Multiplication 🟢 mature
GEMM supported on all inference engines
MoE routing
MoE Routing 🟢 mature
MoE gating supported via vLLM ≥0.4 / SGLang
Normalization
RMSNorm 🟢 mature
fused into engine kernels
Embedding
Rotary Position Embedding 🟢 mature
fused into engine kernels
Activation
SiLU / Swish 🟢 mature
fused into engine kernels
Softmax 🟢 mature
fused into engine kernels

最接近的替代卡 (按规格相似度)

基于 BF16 算力 / 显存 / 显存带宽 / FP8 加权欧氏距离。供选型决策参考。

沐曦 曦云 C500
沐曦
100%
相似度
BF16
128
Mem
64
BW
1.8
燧原 云燧 T21
燧原科技
100%
相似度
BF16
192
Mem
64
BW
1.6
寒武纪 思元 590
寒武纪
100%
相似度
BF16
256
Mem
64
BW
1.2
壁仞 BR100
壁仞科技
100%
相似度
BF16
256
Mem
64
BW
2.3

Software-stack support

Engine Status BF16FP16FP4FP8 E4M3FP8 E5M2INT4 AWQ
HanGuangAI unconfirmed — — — — — —
LMDeploy unconfirmed — — — — — —
MindIE unconfirmed — — — — — —
MoRI unconfirmed — — — — — —
SGLang unconfirmed — — — — — —
TensorRT-LLM (Dynamo) unconfirmed — — — — — —
vLLM community — ✓ — — — —

Existing deployment cases (0)

No measured cases yet for this card. Be the first contributor?

Citations

  1. [1] Hygon DCU product overview (limited detail public) — https://www.hygon.cn/ · accessed 2026-04-28 厂商声称
  2. [2] Z100 (深算一号) is GCN-derived: 64 CUs, 4× HBM2e stacks ⇒ 64 GB; chiplet design at SMIC 7nm-class. Programmed via DTK / HIP (AMD ROCm fork). — https://www.hygon.cn/ · accessed 2026-04-28 社区估算
⚠ All performance figures are vendor-claimed unless tier=measured.
⚠ Hygon DCU uses HIP, similar programming model to AMD ROCm.