NVIDIA R200 SXM (Vera Rubin)
SXM announced 发布于 2026 rubin-gen1
BF16
TFLOP/s
7500 厂商声称
FP8
TFLOP/s
15000 厂商声称
FP4
TFLOP/s
30000 厂商声称
Memory
GB
288 厂商声称
Mem BW
GB/s
13000 厂商声称
TDP
W
1800 厂商声称
完整规格
算力
FP4 TFLOPS
30000
FP8 TFLOPS
15000
BF16 TFLOPS
7500
FP16 TFLOPS
7500
INT8 TOPS
15000
显存
容量
288 GB
带宽
13000 GB/s
类型
HBM4
芯片架构 🟢 vendor floorplan
SM count
200
Tensor cores / SM
4
L2 cache
128 MB
HBM stacks
8
制程
3 nm
PCIe
Gen 6 ×16
Scale-Up (节点内)
协议
NVLink-6.0
单链带宽
3600 GB/s
World size
144
拓扑
switched
交换机
nvswitch-gen5
Scale-Out (节点间)
单卡出口
1600 Gbps
协议
InfiniBand-XDR
NIC
ConnectX-9
拓扑示意
拓扑结构 · Topology
144 卡 scale-up domain
芯片内部 / Die-level architecture
🟢 vendor floorplan 200 SMs · 8× HBM · 128 MB L2 · 3 nm
集群拓扑 / Cluster topology · NVLink-6.0 @ 3600 GB/s
Scale-Up · 域内
NVLink-6.0
3600 GB/s · 拓扑: switched
world_size = 144
Scale-Out · 跨域
InfiniBand-XDR
1600 Gbps/卡 NIC
ConnectX-9
能跑哪些模型?
Quick estimates · decode tok/s/card 上界
TP=8 · FP4 · batch=16 · prefill=1024 · decode=256 · 已应用 efficiency 校准
| 模型 | 参数 (active) | Decode tok/s/card | 瓶颈 |
|---|---|---|---|
| DeepSeek V4 Pro deepseek | 49B | 265,306 | 内存带宽 |
| DeepSeek V4 Flash deepseek | 13B | 370 | 内存带宽 |
| Mistral Small 4 mistral | 22B | 168 | 内存带宽 |
| GLM-5 Reasoning zhipu | 32B | 139 | 内存带宽 |
| GLM-5.1 zhipu | 32B | 95 | 内存带宽 |
| Qwen3.6 Plus alibaba | 35B | 91 | 内存带宽 |
| Kimi K2.6 moonshot | 32B | 78 | 内存带宽 |
| MiniMax M2.7 minimax | 46B | 61 | 内存带宽 |
算子级 fit · 任意模型瓶颈类型 + 上界
算子级 fit · operator-level fit (per-token roofline)
基于每个模型 operator_decomposition + 本卡 BF16 7,500 TFLOPS / 13,000 GB/s 计算 · ridge point ≈ 577 FLOPs/byte
| 模型 | domain | 主导算子 | AI · F/B | 瓶颈 | tok/s 上界 |
|---|---|---|---|---|---|
| DeepSeek V4 Pro | llm | matmul | 245.5 | 💾 内存带宽 | 531k |
| GraphCast | scientific | graph-message-passing | 0.9 | 💾 内存带宽 | 24k |
| AlphaFold 3 | scientific | pair-bias-attention | 2.3 | 💾 内存带宽 | 7206 |
| GPT-OSS | llm | matmul | 0.7 | 💾 内存带宽 | 1051 |
| Gemma 4 26B | llm | matmul | 0.7 | 💾 内存带宽 | 781 |
| DeepSeek V4 Flash | llm | matmul | 0.8 | 💾 内存带宽 | 739 |
| Mistral Small 4 | llm | matmul | 0.6 | 💾 内存带宽 | 337 |
| Llama 4 Maverick | llm | matmul | 0.8 | 💾 内存带宽 | 333 |
需要 efficiency 校准 + concurrency 扫描 + TCO 估算 → 在计算器中评估 →
算子支持 & 优化空间
算子支持 & 优化空间 / Operator support & headroom
Per-operator support derived from software_support.engines + scale-up topology. Optimization headroom from measured efficiency factor.
Optimization headroom
+50 pp
moderate
No cases yet — using default 0.5 efficiency. Real headroom unknown until first measurement lands.
Communication (collective)
All-to-All 🟢 mature
all-to-all via NVLink-6.0 world_size=144
AllReduce 🟢 mature
NVLink-6.0 ring all-reduce
Attention
Multi-Head Attention 🟢 mature
paged-attention via vLLM/SGLang/MindIE
FlashAttention-3 🟢 mature
FA-3 on modern engine + tensor cores
Matrix multiply (GEMM)
Matrix Multiplication 🟢 mature
GEMM supported on all inference engines
MoE routing
MoE Routing 🟢 mature
MoE gating supported via vLLM ≥0.4 / SGLang
Normalization
RMSNorm 🟢 mature
fused into engine kernels
Embedding
Rotary Position Embedding 🟢 mature
fused into engine kernels
Activation
SiLU / Swish 🟢 mature
fused into engine kernels
Softmax 🟢 mature
fused into engine kernels
最接近的替代卡 (按规格相似度)
基于 BF16 算力 / 显存 / 显存带宽 / FP8 加权欧氏距离。供选型决策参考。
软件栈支持
| 引擎 | 状态 | BF16 | FP16 | FP4 | FP8 E4M3 | FP8 E5M2 | INT4 AWQ |
|---|---|---|---|---|---|---|---|
| HanGuangAI | 未确认 | — | — | — | — | — | — |
| LMDeploy | 未确认 | — | — | — | — | — | — |
| MindIE | 未确认 | — | — | — | — | — | — |
| MoRI | 未确认 | — | — | — | — | — | — |
| SGLang | 未确认 | — | — | — | — | — | — |
| TensorRT-LLM (Dynamo) | 官方 | ✓ | ✓ | ✓ | ✓ | ✓ | — |
| vLLM | 官方 | ✓ | ✓ | ✓ | ✓ | ✓ | — |
已有部署案例 (0)
暂无该硬件的实测案例。
成为第一个贡献者?
引证
- [1] NVIDIA Rubin announcement (Computex 2025): NVLink-6.0 at 3.6 TB/s, NVL144 rack-scale, HBM4 with 288 GB / 13 TB/s. Vendor-claimed; not yet GA. — https://www.nvidia.com/en-us/data-center/rubin/ · 访问于 2026-04-29 厂商声称
- [2] Rubin die: 200 SMs enabled, 128 MB L2, dual-die package on TSMC 3nm. Specs estimated from public roadmap; subject to change at GA. — https://www.semianalysis.com/p/rubin-architecture-deep-dive · 访问于 2026-04-29 社区估算
⚠ Status: announced — not yet in customer hands. Specs sourced from Computex 2025 keynote; subject to revision at GA.
⚠ NVL144 super-pod (144 R200 in one scale-up domain) is planned for 2026 H2.